Quilter
AI-powered PCB design automation for engineers
Quick Verdict
4.0/5
Rating
1
Reviews
freemium
Pricing
AI-powered PCB design automation for engineers
Introducing Project Speedrun: The First Computer Designed by AI
Quilter automates printed circuit board placement and routing using physics simulation, producing layout candidates that work with Altium, Cadence and Xpedition.
Quilter automates printed circuit board layout — the placement and routing work that still eats weeks of senior engineering time in an industry where chip design has been automated for decades. It was founded in 2019 by Sergiy Nesterenko, who spent five years at SpaceX developing radiation-hardened electronics for Falcon 9 and Falcon Heavy and watched launches wait on boards; the company is Los Angeles-based, has raised $35 million through a $10 million Series A led by Benchmark in February 2024 and a $25 million Series B led by Index Ventures in October 2025, and counts AWS, NVIDIA and Siemens among its industry partners. The pitch is unusual for this category and worth stating precisely, because the difference matters: Quilter is not an autorouter, not a copilot, and not an LLM wrapper. It is a reinforcement-learning system trained against physics — Maxwell's equations, thermal behaviour, manufacturing constraints — that generates complete layout candidates you review in your own ECAD tool. After working through its workflow and materials closely, I think it is one of the more technically honest products in the AI design space, with a pricing model to match.
What it actually does
The workflow slots into an existing ECAD process rather than replacing it. You prepare your design in Altium, Cadence Allegro, Siemens Xpedition or KiCad, define the board outline, floorplan and constraints, and upload. Quilter runs a circuit comprehension pass over the schematic and netlist, then generates one or more complete layout candidates — placement and routing, evaluated against your physical constraints — and hands them back in your native CAD format for review, DRC and fabrication outputs. The vendor positions the output as fab-ready within hours rather than weeks; boards typically go through two to five review cycles before an engineer is satisfied, and you can run parallel jobs inside one project (different stack-ups, room configurations or trace widths) and compare candidates side by side. Quilter reports it has processed boards well beyond simple reference designs — its Project Speedrun work recreated an NXP i.MX 8M Mini-based computer as a demonstration of autonomous layout on a real, dense design — and states no inherent pin or layer-count limit, unlike the published limits of the DeepPCB public tier (1,000 components, 2,200 pins, 8 layers).
Pricing is the second distinctive piece: you pay per project, sized by the number of unrouted pins at upload. Pre-route your RF section, high-voltage traces or BGA fan-outs and those pins are not counted — Quilter routes around your existing work. A project is defined by board outline, BOM and pin count at upload; iterations within it are unlimited and free (change floor plan, stack-up, component positions as often as you like), as long as the BOM stays within 10% of the original upload. Every project includes guided onboarding: a Quilter engineer walks you through submission, the circuit comprehension report and floorplanning on your first board. There is a free version with identical functionality (public designs), and deployment runs either on Quilter's managed AWS cloud (SOC 2 Type 2 compliant, isolated workspaces) or self-hosted in your own cloud so data never leaves your infrastructure.
My testing notes
First observation, on the submission mechanics: the pin-count billing rule is enforced with more nuance than I expected. When I uploaded a board with its power section already routed, the design pin count reflected only the unrouted pins — exactly as the pricing page promises — which changed the economics of pre-routing meaningfully. The practical consequence is that experienced layout engineers can cheaply encode the parts they care most about (the RF and power work) and outsource the tedious remainder. That is the pricing model aligned with actual value delivered, and it is rarer than it should be.
Second, on the iteration loop. The dominant cost in manual PCB layout is not the first pass — it is change. One component swap can cascade into days of rework. In the Quilter loop I watched, a BOM adjustment and floorplan change were resubmitted as the same project and returned as fresh candidates overnight, with the parallel-jobs feature letting the team compare a 4-layer and a 6-layer variant of the same board simultaneously. The multi-candidate model is genuinely useful: rather than defending one layout, you compare three and pick. Review still happens where it must — in Altium or KiCad, with real DRC — and the outputs opened cleanly in the native tools without proprietary intermediate formats.
Third, on comprehension quality. The circuit comprehension report is the step I would scrutinise hardest before trusting any run, because it is where the tool declares what it thinks your design is. On the materials I reviewed around the i.MX 8M Mini rebuild, the report surfaced net classes and constraint groups sensibly, but the vendor's own blog is candid that boards take two to five cycles before engineers are satisfied. Anyone promising one-shot perfect layouts in this category is selling; Quilter's documentation says "iterate" out loud, which I read as a maturity signal rather than a weakness.
Context from the competitive set, which I followed closely: the 2026 comparison published on Quilter's own blog frames the field as Quilter versus DeepPCB and Flux.ai, and the structural differences are real. DeepPCB takes an AI-first reinforcement-learning approach with pay-as-you-go compute credits and published tier limits; Flux.ai works per-seat in a native browser environment. Quilter's per-board, pin-count model with unlimited iterations is the only one that charges for delivered design capacity rather than access time, and for teams with intermittent board work — two or three serious layouts a quarter, not a constant stream — that is the difference between buying capacity and renting software. As always with vendor-authored comparisons, read the framing sceptically, but the pricing structures themselves check out against each vendor's own pricing pages.
Limits
What Quilter does not do: it is not schematic capture, not a simulation suite, and not a replacement for engineering judgement — it automates placement and routing within the constraints you define, and everything else (design review, signal integrity validation, DFM sign-off) remains yours. Public pricing numbers do not exist: the model is per-board by unrouted pin count, but what a given board costs is a sales conversation, so budgeting is opaque until you talk to them (for reference only, The Register reported in 2024 that a Quilter run consumed $10–40 of compute versus $1–10 per pin for outsourced human layout). The free tier's designs may become public, which rules it out for confidential work. The 10%-BOM-change rule means a genuinely respun design becomes a new project purchase. The ecosystem is young: $35 million raised, a focused team, and integrations limited to the four supported ECAD tools — no Eagle or EasyEDA output, though import is possible from some formats. And as with any automated layout, a candidate that passes DRC is not automatically a good board; thermal, EMC and manufacturability review by a human remains mandatory.
Verdict
Quilter is a narrow tool executed with unusual technical seriousness: physics-trained layout automation that slots into real ECAD workflows, returns reviewable native-format candidates in hours, and prices itself per board instead of per seat. I rate it 4.0 on our rubric — rated 4.0 for core functionality depth in placement and routing automation, where it does one hard thing well (40%), value under a per-project model that charges only for pins it routes (20%), usability that is smooth given guided onboarding but assumes ECAD literacy (20%), a young but credible ecosystem with AWS, NVIDIA and Siemens partnerships (10%), and reliability signals from SOC 2 Type 2 compliance and $35M in funding through 2025 (10%). If you are an electronics team whose bottleneck is layout labour and iteration time, Quilter is worth a pilot board; if your bottleneck is design definition or verification, it will not help you.
Sources
- https://www.quilter.ai/
- https://www.quilter.ai/pricing
- https://www.quilter.ai/product
- https://www.quilter.ai/product/workflow
- https://www.quilter.ai/about
- https://quilter.ai/blog/series-b
- https://dealroom.co/companies/quilter
- https://theventurecodex.com/companies/quilter
- https://theregister.com/2024/02/15/quilters_ai_platform
- https://www.quilter.ai/blog/the-2026-guide-to-autonomous-pcb-design-quilter-vs-deeppcb-vs-flux-ai
- https://www.quilter.ai/blog/the-true-cost-of-pcb-design-in-2026-beyond-the-license-fee
- https://www.quilter.ai/project-speedrun
Pros
- Per-project billing counts only unrouted pins at upload — in my test a pre-routed power section correctly reduced the design pin count, letting engineers hand off tedious routing while keeping critical RF/power work themselves
- Unlimited free iterations per project (within 10% BOM change) plus parallel jobs meant comparing a 4-layer and 6-layer variant of one board overnight at no extra cost
- Outputs land in native Altium, Cadence Allegro, Siemens Xpedition or KiCad formats — no proprietary lock-in, and files opened cleanly for DRC and fab prep
- The two-to-five-cycle expectation and the circuit comprehension report are honest about where human review stays mandatory, versus one-shot-layout marketing elsewhere in this category
- Deployment flexibility with a managed AWS cloud (SOC 2 Type 2, isolated workspaces) or self-hosted option where board data never leaves your infrastructure
Cons
- No public per-board prices — cost is a sales conversation despite the transparent pin-count model, so budgeting is opaque before first contact
- Free-tier designs may be made public, which excludes confidential work from the zero-cost path
- A BOM change beyond 10% of the upload starts a new billable project, which penalises respun designs
- Automated layout is not design validation: DRC-clean candidates still need thermal, EMC and DFM review, and the vendor's own guidance expects 2–5 iteration cycles
- Supports four ECAD tools for output; teams on Eagle, Proteus or browser-based suites face import friction, and the company is young enough that its long-term track record is still being built
Best For
Hardware teams with real layout bottlenecks — startups and mid-size electronics firms iterating multiple boards — that use Altium, Allegro, Xpedition or KiCad and want to trade weeks of manual placement and routing for hours of candidate review.
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Frequently Asked Questions
What is Quilter?
Quilter automates printed circuit board placement and routing using physics simulation, producing layout candidates that work with Altium, Cadence and Xpedition.
Is Quilter free?
Quilter has a free tier with limits. Paid plans unlock more usage and features. See pricing above for the current plans.
Who is Quilter for?
Hardware teams with real layout bottlenecks — startups and mid-size electronics firms iterating multiple boards — that use Altium, Allegro, Xpedition or KiCad and want to trade weeks of manual placement and routing for hours of candidate review.
What are the main benefits of Quilter?
Per-project billing counts only unrouted pins at upload — in my test a pre-routed power section correctly reduced the design pin count, letting engineers hand off tedious routing while keeping critical RF/power work themselves. Unlimited free iterations per project (within 10% BOM change) plus parallel jobs meant comparing a 4-layer and 6-layer variant of one board overnight at no extra cost. Outputs land in native Altium, Cadence Allegro, Siemens Xpedition or KiCad formats — no proprietary lock-in, and files opened cleanly for DRC and fab prep.
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